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Present (since 2015, valid up to 2017 so far)

Past (2010-2015)


KBelle Meeting Dec 09 2016 (Yonsei U)
KBelle Meeting Jun 10 2016 (Seoul National U)
2016 K-Belle II Analysis Workshop (Daejeon)
KBelle Meeting Dec 18 2015 (Yonsei U)
KBelle Meeting May 09 2015 (Soongsil U)
KBelle Meeting Dec 05 2014 (KISTI)
KBelle Meeting Aug 22 2014 (GSNU)
KBelle Meeting Jan 06 2014 (Chonnam)
KBelle Meeting May 25 2013 (KNU)
KBelle Meeting Dec 27 2012 (Soongsil U)
KBelle Meeting Aug 17 2012 (Yonsei U)
KBelle Meeting Aug 24 2011 (KISTI)
KBelle Meeting Apr 30 2011 (Hanyang)
KBelle Meeting Dec 11 2010 (SNU)
KBelle Meeting Aug 18 2010 (Yangyang)
KBelle Meeting Jun 25 2009 (SNU)
KBelle Meeting Mar 14 2009 (SNU)

Past (since 2006, valid up to 2008 so far)

We are focuing on the super B factory project which is an extension to the Belle experiment. In particular, we are mainly working on

Past

CP violation studies and the baryon asymmetry we observe today would be the primary research topic that we are interested in. In conjunction with it, we contribute to the readout electronics upgrade for the Belle experiment since 2004. Finally, the Belle readout electronics is going to be fully pipelined system that minimizes the deadtime of the readout due to high rates of the level one trigger. The picture on the left is the local setup for the readout electronics board we are debugging in the Belle experiment. This is to be used for the readout of the entire Belle detector signals. It also serves as readout systems for other experiments in KEK, in particular some of future J-PARC experiments. The board you see is called COPPER (COmmon Pipelined Platform for Electronics Readout) board that may house a PMC card, a homemade trigger receiver board (tt-rx), and FINESSE (Front-end INstrumentation Entity for Sub-detector Specific Electronics) cards that serve as digitizers (TDC or ADC depending on characteristics of the sub-detector associated with). Belle live event display can be found here.
The picture on the left is the board that I have been working on for last two years in the BaBar experiment. This is to be used for the L1 track trigger upgrade project. It does the 3D tracking in 2.2 micro second to reject large z0 tracks originated from the backgrounds. As you can see from it, there are 8 Xilinx FPGA chips (Vertex II) on the board, doing the decoding, 3D finding/fitting, and making a set of decisions based on the fit results. Lots of VHDL programs were written by me and another postdoc from Harvard. On the top-left, you see a flash memory card (The one that you have in your digital camera) that holds the firmware to be loaded. If you are familiar with this kind of stuff, you must have noticed that this 9U Eurocard has not much on the board (usually lots of termination resistor and capacitor arrays are connected in very complicated way). Thanks to the modern cutting edge technology, they are mostly now in the FPGA chips. Six parallel chips on the top left run at the speed of 120 MHz and rest of two at 60 MHz. This board is conceptually similar to the one ( CCM ) on which I worked previously but the current one is far more complicated. If you can build something like this, you can build your own cellular phone yourself :-)!