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The picture on the left is the board that I have been working on for
last two years
in the BaBar experiment.
This is to be used for the
L1 track trigger upgrade project. It does the 3D tracking in 2.2
micro second to reject large z0 tracks originated from the backgrounds.
As you can see from it, there are 8
Xilinx FPGA chips (Vertex II) on the board, doing the decoding,
3D finding/fitting, and making a set of decisions based on the
fit results. Lots of VHDL programs were written by me and another
postdoc from Harvard. On the top-left, you see a flash memory
card (The one that you have in your digital camera) that holds the
firmware to be loaded. If you are familiar with this kind of stuff,
you must have noticed that this 9U Eurocard has not much on the
board (usually lots of termination resistor and capacitor arrays
are connected in very complicated way).
Thanks to the modern cutting edge technology, they are mostly now
in the FPGA chips. Six parallel chips on the top left run at the
speed of 120 MHz and rest of two at 60 MHz. This board is conceptually
similar to the one (
CCM
) on which I worked previously
but the current one is far more complicated. If you can build
something like this, you can build your own cellular phone yourself :-)!
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